SUMMARY OF QUALIFICATIONS:
Results-driven Technology Director, well-versed in CMOS and BiCMOS technologies ranging from 0.5um to < 90nm level. Managed or contributed to success of over 2 dozen vertically-integrated process technologies across more than a dozen product lines including MPU, MCU, EPROM, EEPROM, flash, SRAM, DPRAM, TCAM, analog, logic and gate array. Technology and management skills:
* Project Manager showing leadership in start-to-finish technology development, both direct and dotted-line management, both internal technology development and foundry management.
* Cross-functional team leader who drives solutions through inter-departmental cooperation.
* Demonstrated versatility in moving across projects and technologies, and changing roles within a project as needed.
* Experience with stand-alone and integrated MEMS.
* Developing alternative methods for Solid-State Drive (SSD) usage, using ST-RAM/ReRAM, 3-D technologies, vertical transistors and wafer bonding.
* Seasoned in competitive chip and IP analysis and application to improved designs and cost structures.
* Device engineering of physically meaningful SPICE models used for both active and passive devices. Developed E=M methodology, resulting in device models useful to design, technology and manufacturing.
* Test chip management: e-test structure definition, layout, verification, fabrication and testing.
* Integration engineer with complete understanding of horizontal and vertical technology constraints, topographical design rule generation and checking, SPC, DOE, and DFM.
* Thorough understanding of reliability physics mechanisms and their role in determining product quality. Developed chip-level ESD and latchup protection designs.
TECHNICAL SKILLS:
* Project management using Microsoft Project.
* Studying for PMP certification (expected end-2009)
* Statistical design methods--SPC, DOE, DFM
* Engineering analysis--RS/1, JMP
* Silvaco SPICE model generation tools--UTMOST, SmartSpice
* TCAD--SUPREM3, SUPREM4, DEPICT
* HP BASIC--debugging and reworking e-test code
* Cadence and Mentor design tools--layout, schematic, DRC, LVS, extractions
* PC-based layout tools--basic knowledge of L-edit, S-edit
* Unix--basic knowledge
* MS Office--Word, Excel, PowerPoint, Visio
PROFESSIONAL EXPERIENCE:
Seagate Technology, Bloomington MN, 2008-present
Technologist, Advanced Technology Group
Development of SSD's using Spin Torque RAM (ST-RAM) and Resistive RAM (ReRAM) technology. Managed cross-functional issues related to design, technology and CAD
* Authored platform project management methodology, enabling integration of multiple functional teams (e.g. product/test, process, design and marketing), external (foundry) and in-house fabs, and outside design houses.
* Implemented robust design rules, e-test structures used to refine cell-based rules, and frame build for emerging memory products.
* Developing 3-D integration methods using wafer bonding and vertical transistor technologies.
Silicon Light Machines (Cypress MEMS subsidiary), San Jose CA, 2006-2008
Technology Development Engr MTS
Acted as "CMOS expert" in a group of "MEMS experts", to improve yield on a 0.6um integrated optical MEMS technology using LD-NMOS and conventional CMOS processing in Cypress Texas fab.
* Acted as Project Manager (PM) for critical design project. Directed cross-functional teams to bring product through pilot production, enabling entry into gaming mouse market.
* Due to Cypress fab closure, became Project Manager for team evaluating foundry alternatives. Upon sale of company, transitioned to consulting role, transferring project to another manager mid-2008.
Cypress Semiconductor, Bloomington MN, 2001-2006
Technology Development Eng Director/MTS
Started as technology director in Data Communications Division. Directed foundry liaison group making Complex Programmable Logic Devices (CPLD) at the 180 nm technology node.
* Improved 39K CPLD yield from 40% to >70% and ESD (HBM) failing voltages from <1100 V to >2200 V; enabled product transfer to full production at foundry.
* In order to reduce reliance on human design rule checking (DRC), chaired cross-functional team (CFT) implementing ESD design methodology changes. Ultimately improved automated DRC chip coverage from <40% to >80%.
Transferred to R&D group to develop 0.24um SiGe BiCMOS process for high-speed PHY applications.
* Responsible for project planning, technical management, budgeting of manpower and materials, and weekly updates to Senior Management.
* Worked with outside design/technology consultants to bring engineering team members up to speed.
* Started out with device/integration teams and moved into PM role, managed project into production.
Project Manager and Technical Lead of 90nm technology platform, implemented across 4 different product lines in 2 divisions. Started technology development from project's inception, transitioned into Technical Lead role, as "go to" guy for all things related to the technology.
* In order to "break down walls" between functional groups, chaired 3 CFT's across multiple sites. The "Design/Technology/CAD" group became most successful CFT within the company, integrating concurrent engineering goals and enabling faster product development.
* Project Manager of 2 test chip projects, 1st with external design house, the 2nd internally done, to enable design rule evaluation, electrical model and defect density extractions, and memory cell optimization.
* To reduce amount of "over-design" required in baseline IP, co-developed "E=M" as the chair of a CFT which encompassed all the Design groups, Operations, CAD, Modeling and Technology. This enabled smooth integration of e-test spec limits (e.g. NMOS Vt) with Spice model parameters (e.g. VTH0) and manufacturing specs (e.g. gate oxide TOX, poly-Si gate CD)
* As 90nm project neared full production transfer, company elected to discontinue future process R&D. Transferred to Silicon Light Machines subsidiary at the end of 2006.
Zilog (Nampa ID), 1996-2000
Director, Device Technology
Returned to Zilog in 1996 as manager of R&D device group. Promoted to Director in 1998 and later served on cross-company strategy teams.
* Significantly reduced field fails, implemented design changes improving ESD (HBM) from <2000V to >8000V and latchup trigger currents from <200mA to >1000mA, across all CMOS products.
* Directed competitive analysis--coordinating product line, technology and FA personnel to understand cost-effective design and process improvements.
* Drove development of all Spice-compatible device models used by design teams, development and implementation of topographical design rules, and design of all e-test structures to verify same. Initiated methods to link e-test and device model parameters.
* Directed test chip design and device model development for 0.35um embedded NVM technology currently in use at leading foundry.
Micron Technology (Boise ID), 1993-1996
Principal Flash Engineer
Accepted pre-public opportunity at Micron Quantum Devices (later bought by Micron Tech) in late 1993. Functioned as individual contributor in NOR flash memory development team, initially on 0.8um and later on 0.6um technology.
* Conducted design rule evaluation, dielectric and cell shrink, and cell reliability testing to optimize cell size and operating vovltages for flash memory read, write and erase conditions.
* Implemented RSS (root-sum-squared) methodology to evaluate topographical design rules, developed simple device models for cell evaluation.
* Conducted e-test, "disturb" testing and single-bit charge loss efforts resulting in a 10X reduction in data retention loss over a 6-month period.
Zilog (Nampa ID), 1991-1993
Process Integration Manager
Managed process integration group directly, dotted-line management of unit process development team to achieve technology goals. Responsible for detailed project management from inception to final production transfer.
* Developed 0.8um node process technologies including logic, analog, ROM and OTP derivatives.
* Headed up a cross-functional (design, operations and technology) task force which improved 1.2um node product yield by 40% within a 6-month time frame.
ADDITIONAL EXPERIENCE:
United Technologies Microelectronics Center (Colorado Springs CO), 1990-1991
(captive fab/design house for United Technologies Corp)
Principal Process Integration Engineer
Developed DLM/TLM backend process technologies for military/aerospace applications.
Motorola (Austin TX), 1986-1990
Device Engineering Section Manager, APRDL (1988-1990)
Senior Device Engineer, APRDL (1986-1988)
Developed DLM/TLM process technologies for mixed-signal and gate array applications.
Advanced Micro Devices (Sunnyvale CA), 1981-1986
Senior Process Development Engineer, EPROM technology development (1984-1986)
Process Development Engineer, EPROM technology development (1981-1984)
Developed EPROM technologies at the 3.0, 2.0, and 1.5 um nodes
EDUCATION:
Cornell University, Ithaca, NY
Master of Engineering in Engineering Physics (1981)
Bachelor of Arts in Physics (1980)
ADDITIONAL COURSEWORK:
University of St. Thomas, mini-MBA program, 2009
UCLA course on Image Sensor process, design, and test, 2006
Project Management coursework, 2003
MIT graduate course on Analog IC Design, 2000
ESD Tutorial taken through ESD Association, 1996
2 UC Berkeley short courses (MOS device physics, MOS analog IC's), 1987-88
4 Stanford graduate courses (device physics, crystalline solids, photolithography), 1982-84
PROFESSIONAL ASSOCIATIONS:
IEEE Electron Devices, Solid-State Circuits, Engineering Management Societies (current memberships)
IEEE Standards Association (past member)
ESD Association (past member)
PUBLICATIONS:
I. Polishchuk, P. Manos, et.al, "Implant process modifications for suppressing WPE", Solid State Technology, Apr. 2006
I. Polishchuk, P. Manos, et.al, "CMOS Vt control improvement through implant lateral scatter elimination", 2005 Int'l Symp on Semiconductor Manufacturing
P. Manos and H.A. Stevens, "Effects of backend processing on counter-doped N+ poly-Si resistance", IEEE Trans Semi Manuf, Nov. 1991
P. Manos and C. Hart, "A self-aligned EPROM structure with superior data retention", IEEE Elect Dev Lett, July 1990
P. Manos, et.al, "A submicron CMOS triple-level metal gate array process utilizing tungsten for 1st level interconnect", 1989 VLSI Multilevel Interconnect Conferance, Santa Clara, CA
P. Manos, et.al, "Process, fabrication, and characteristics of a 0.8um CMOS triple-level metal gate array", 1989 Symp on VLSI Tech, Syst and Apps, Taipei, Taiwan
S. Cheng and P. Manos, "Effects of operating temperature on electrical parameters in an analog process", IEEE Circuits and Devices, July 1989
J. Lien, P. Manos, et.al, "A high performance CMOS process for the next generation EPROM", 1984 IEDM Technical Digest
PATENTS: 4 pending (filed in 2009), 7 issued
6,300,796 "High voltage PMOS level shifter", B. Troutman and P. Manos, issued 10/9/01
5,631,180 "Method of fabricating high threshold metal oxide silicon read-only-memory transistors", A. Gyure, J. Berg, D. Carver, and P. Manos, issued 5/20/97
5,498,896 "Method of fabricating high threshold metal oxide silicon read-only-memory transistors", A. Gyure, J. Berg, D. Carver, and P. Manos, issued 3/12/96
5,389,565 "Method of fabricating high threshold metal oxide silicon read-only-memory transistors", A. Gyure, J. Berg, D. Carver, and P. Manos, issued 2/14/95
5,317,187 "Ti/TiN/Ti contact metallization", G. Hindman, J. Berg, and P. Manos, issued 5/31/94
5,240,880 "Ti/TiN/Ti contact metallization", G. Hindman, J. Berg, and P. Manos, issued 8/31/93
4,982,250 "Moisture barrier for floating gate transistors", P. Manos and R. Countryman, issued 1/1/91 |
